2.5.1.4 Exceptions and Interrupts

The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses Handler mode to handle all exceptions except for reset. For more information, see 2.5.3.7.1 Exception Entry and 2.5.3.7.2 Exception Return.

The NVIC registers control interrupt handling. For more information, see 2.4.1 Nested Vectored Interrupt Controller.

The following sections provide more information about the CMSIS.

• 2.5.5.5 Power Management Programming Hints
• 2.6.2 CMSIS Functions
• 2.7.1.2 Accessing the Cortex-M3 Processor NVIC Registers Using CMSIS
• 2.7.1.11.1 NVIC programming hints