2.7.1.2 Accessing the Cortex-M3 Processor NVIC Registers Using CMSIS

CMSIS functions enable software portability between different Cortex-M3 profile processors. To access the NVIC registers when using CMSIS, use the following functions:

Table 2-35. CMSIS Access NVIC Functions
CMSIS Function	Description
void NVIC_EnableIRQ(IRQn_Type IRQn)¹	Enables an interrupt or exception.
void NVIC_DisableIRQ(IRQn_Type IRQn)^a	Disables an interrupt or exception.
void NVIC_SetPendingIRQ(IRQn_Type IRQn)^a	Sets the pending status of interrupt or exception to 1.
void NVIC_ClearPendingIRQ(IRQn_Type IRQn)^a	Clears the pending status of interrupt or exception to 0.
uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)^a	Reads the pending status of interrupt or exception.  This function returns non-zero value if the pending status is set to 1.
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)^a	Sets the priority of an interrupt or exception with configurable priority level to 1.
uint32_t NVIC_GetPriority(IRQn_Type IRQn)^a	Reads the priority of an interrupt or exception with configurable priority level. This function return the current priority level.

Note:

The input parameter IRQn is the IRQ number, see Table 22 on page 34 for more information.