2.5.1.3 Core Registers

The following figure shows the processor core registers.

Figure 2-2. Core Register Set

Table 2-2. Core Register Set Summary
Name	Type¹	Required Privilege²	Reset Value	Description
R0-R12	RW	Either	Unknown	General-Purpose Registers
MSP	RW	Privileged	See description	Stack Pointer
PSP	RW	Either	Unknown	Stack Pointer
LR	RW	Either	0xFFFFFFFF	Link Register
PC	RW	Either	See description	Program Counter
PSR	RW	Privileged	Unknown	Program Status Register
ASPR	RW	Either	Unknown	Application Program Status Register
IPSR	RO	Privileged	0x00000000	Interrupt Program Status Register
EPSR	RO	Privileged	0x01000000	Execution Program Status Register
PRIMASK	RW	Privileged	0x00000000	Priority Mask Register
FAULTMASK	RW	Privileged	0x00000000	Fault Mask Register
BASEPRI	RW	Privileged	0x00000000	Base Priority Mask Register
CONTROL	RW	Privileged	0x00000000	CONTROL Register

Note:

Describes access type during program execution in Thread mode and Handler mode. Debug access can differ.
An entry of Either means privileged and unprivileged software can access the register.

The following sections describe these registers in detail.

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