8.2.1.3 Timing and Control

The peripheral ready signals (for example, RxRDY and TxRDY in MMUART) from the SPI, MMUART, COMM_BLK, and CAN are directly connected to the PDMA. The ready signals from the CAN are not used and are tied to logic 1, internally. The PDMA takes care of writing or reading the receive or transmit holding registers within each peripheral using the APB interface.

The DMAREADY_0 and DMAREADY_1 signals correspond to the ready signals from the fabric peripheral. If the channel is configured for peripheral DMA and the direction is from the fabric peripheral to memory, this signal indicates that the fabric peripheral can write data to memory. If the channel is configured for peripheral DMA and the direction is from memory to the fabric peripheral, this signal indicates that the fabric peripheral can read data from memory. The PDMA does not support peripheral to peripheral data transfer, scatter-gather DMA, and I²C DMA.