8.2.1.2 8-Channel DMA Controller

The 8-channel DMA controller consists of eight instances of a single DMA channel, as shown in the preceding figure. Each channel can be configured to perform 8-bit, 16-bit, or 32-bit data transfers from the peripheral to memory, memory to peripheral, and memory to memory. Each DMA channel supports Ping-pong mode for continuous data transfer. To enable and use PDMA services, the AHB bus master matrix must configure the following 32-bit registers.

• 8.4.1.3 CHANNEL_x_CONTROL Register Bit Definition (Table 8-7)
• 8.4.1.5 CHANNEL_x_BUFFER_A_SRC_ADDR Register Bit Definition (Table 8-10)
• 8.4.1.6 CHANNEL_x_BUFFER_A_DST_ADDR Register Bit Definition (Table 8-11)
• 8.4.1.7 CHANNEL_x_BUFFER_A_TRANSFER_COUNT Register Bit Definition (Table 8-12)
• 8.4.1.8 CHANNEL_x_BUFFER_B_SRC_ADDR Register Bit Definition (Table 8-13)
• 8.4.1.9 CHANNEL_x_BUFFER_B_DST_ADDR Register Bit Definition (Table 8-14)
• 8.4.1.10 CHANNEL_x_BUFFER_B_TRANSFER_COUNT Register Bit Definition (Table 8-15)

If bidirectional DMA of peripheral to memory (receive) and memory to peripheral (transmit) is desired, two channels must be programmed appropriately. In particular, the TRANSFER_SIZE fields in both the Table 8-7 registers must be programmed identically. The PDMA performs the correct byte lane adjustments appropriate to the address being used on the AHB. Efficient use of memory storage is achieved in this manner, even if only performing byte or 16-bit accesses to or from a peripheral. For example, when the PDMA is accessing peripherals, the lowest 8 or 16 bits of the data bus are always used for 8-bit or 16-bit transfers. For 32-bit transfers, the full 32-bits are used. It is possible to configure the data width of a transfer to be independent of the address increment. The address increment at both ends of the DMA transfer can be different, which is required when reading from a peripheral holding register (single address) and writing to memory incrementally (many addresses).

Sixteen possible channels are available to the PDMA, as listed below. Only eight are used simultaneously.

• MMUART_0 to any MSS memory-mapped location
• Any MSS memory-mapped location to MMUART_0
• MMUART_1 to any MSS memory-mapped location
• Any MSS memory-mapped location to MMUART_1
• SPI_0 to any MSS memory-mapped location
• Any MSS memory-mapped location to SPI_0
• SPI_1 to any MSS memory-mapped location
• Any MSS memory-mapped location to SPI_1
• FPGA fabric peripheral on FIC_0 to any MSS memory-mapped location
• Any MSS memory-mapped location to FPGA fabric peripheral on FIC_0
• CAN to any MSS memory-mapped location
• Any MSS memory-mapped location to CAN
• FPGA fabric peripheral on FIC_1 to any MSS memory-mapped location
• Any MSS memory-mapped location to FPGA fabric peripheral on FIC_1
• COMM_BLK to any MSS memory-mapped location
• Any MSS memory-mapped locations to COMM_BLK