1.5.2 Cortex-M3 Processor Trace System

The debug system of the Cortex-M3 processor is based on the CoreSight architecture. The 
CoreSight-based designs enable the memory and peripheral registers to be examined even when the CPU is running. It also includes the following trace capabilities:

• Data trace, generating events to record data reads/writes, exceptions/interrupts, and PC (program counter) sampling information.
• Software trace, supporting output of debug messages (for example, printf) to the host.
• Instruction trace, collecting a sequence of every executed instruction continuously for a selected portion of your application.

Trace data can be useful for debugging issues and collecting statistics:

• Locating errors that have irregular symptoms
• Analyzing dynamic system behavior
• Optimizing performance bottlenecks
• Counting code coverage statistics

Trace results are generated in the form of packets, which can be of various lengths. The trace components transfer the packets using the advanced trace bus (ATB) to the TPIU, which formats the packets into the trace interface protocol (TIP). The data is then captured by an external trace capture device such as a trace port analyzer (TPA).

The main components of the Cortex-M3 processor that can be a trace source:

• DWT, for data trace
• ITM, for software trace
• ETM, for full instruction trace

DWT, ITM, and ETM generate trace data in the form of packets and transfer them through the ATB to the TPIU.

The TPIU has two operation modes:

• Clocked mode, using up to 4-bit (1-, 2- or 4-bit) parallel data outputs
• SWV mode, using the single-bit SWO format. Instruction trace from ETM must use the parallel trace port, while packets of data trace and software trace normally use SWO (called SWO trace) but can also be multiplexed with the ETM trace stream through the parallel trace port.

The following figure shows the diagram of a Cortex-M3 processor trace system. JTAG/SWD, SWO, and the 4-bit parallel trace port can be deployed into a 20-pin Cortex Debug + ETM connector on the target.

The following table shows pin multiplexing details for JTAG, SWD, and ETM modes of the debug section. For more details on pin information, refer to the DS0115: SmartFusion2 Pin Descriptions Datasheet.