1.5.1 Cortex-M3 Processor Debug Port

The debug port uses a serial wire (SW) JTAG debug port (SWJ-DP). This enables either the JTAG or the SW protocol to be used for debugging. The SWJ-DP defaults to JTAG mode at power-up and can be switched to SW by applying a specific sequence to the debug pins.

The trace port interface unit (TPIU) is configured to support ITM debug trace and ETM debug trace. Serial wire mode is used for the TPIU output data and this is overlaid on the JTAG TDO port. One implication of this is that instrumentation trace cannot be used along with JTAG-based debugging. SW debugging and ITM can be used together.

The Cortex-M3 processor provides the following debug Interfaces:

  • SWJ-DP: JTAG is the industry-standard interface used to download and debug programs on a target processor, as well as for other functions. It offers access to all of the Cortex-M3 processor CoreSight® debug capabilities.
  • SW-DP: The serial wire debug (SWD) mode is an alternative to the standard JTAG interface. SWD uses two pins to provide the same debug functionality as JTAG with no performance penalty, and introduces data trace capabilities with the serial wire viewer (SWV). The SWD interface pins are overlaid with the JTAG signals, allowing standard target connectors to be used.
    • TCLK: SWCLK (serial wire clock)
    • TMS: SWDIO (serial wire debug data input/output)
    • DO: SWO (output pin for SWV, refer to the next section).
  • SWV: It provides real-time data trace information from various sources within the Cortex-M3 processor device. This is output via the single serial wire output (SWO) pin while your system processor continues running at full speed. SWV can only be used with the SWD interface.
  • ETM: The embedded trace macrocell provides high bandwidth instruction trace via four dedicated trace pins.