13.2.4.3 Interrupts

Interrupts can be set up to signal the completion of a data frame transmission or reception. There is one interrupt signal from each SPI peripheral. The SPI_0_INT signal is generated by SPI_0 and is mapped to INTISR [2] in the Cortex-M3 processor nested vectored interrupt controller (NVIC). The SPI_1_INT signal is generated by SPI_1 and is mapped to INTISR [3] in the Cortex-M3 processor NVIC.