13.2.4.1 SPI Transmit and Receive FIFO Flags

The SPI controller contains two, 4×32 (depth x width) FIFOs, as shown in Figure 13-2. One is for the receive side and the other is for the transmit side. The TXFIFOFUL and TXFIFOEMP bits of the Table 13-11 register indicate the full or empty status of the transmit FIFO. The RXFIFOFUL and RXFIFOEMP bits of the Table 13-11 register indicate the full or empty status of the receive FIFO. User logic can poll these bits to obtain the status of the corresponding FIFO.

For large data transfers, the full depth of transmit FIFO can be used by setting the number of data frames (more than one) in a burst (maximum is 64 k frames). When the interrupts are enabled, the TXDONE bit of the Table 13-19 register is asserted after all the data frames in the burst are sent.

For example, if the data frame size is set to 32 and the count is set to 2, the interrupt TXDONE is generated after every 2 words (each word is 32 bits). The default value for the frame count is 1. The TXUNDERRUN and RXOVERFLOW bits of the Table 13-11 register indicate that a FIFO under-run or FIFO overflow has occurred.