9.2.3.4.1 Host Mode

Where the USB controller is operating in Host mode, the Cortex-M3 processor or fabric master starts the session by setting the session bit of Table 9-52. Power is then applied to VBus and the core waits for a device to be connected. 
When a device is detected, a connect interrupt is generated (the Conn bit in Table 9-16, goes high). The speed of the device that has been connected can be determined by reading Table 9-52, where the FSDev bit will be high for a high speed/full speed device and the LSDev bit will be high for a low speed device. The Cortex-M3 processor or fabric master should then reset the device. If both FSDev and HS Enab (Table 9-11) are set, the USB controller will try to negotiate for high speed operation. Whether this is successful, is indicated by the HS mode bit (Table 9-11).
The Cortex-M3 processor or fabric master should keep the Reset bit set for 20 ms to ensure that the target is reset. It can then begin device enumeration.
If the device is disconnected while a session is in progress, a disconnect interrupt is generated (the DisCon bit in Table 9-16, goes High).