7.7.5 PIE3

Peripheral Interrupt Enable Register 3

Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1-PIE8.
Name: PIE3
Offset: 0x719

Bit 76543210 
   RC1IETX1IEBCL2IESSP2IEBCL1IESSP1IE 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 5 – RCnIE EUSARTn Receive Interrupt Enable bit

ValueDescription
1 Enabled
0 Disabled

Bit 4 – TXnIE EUSARTn Transmit Interrupt Enable bit

ValueDescription
1 Enabled
0 Disabled

Bits 1, 3 – BCLnIE MSSPn Bus Collision Interrupt Enable bit

ValueDescription
1 Enabled
0 Disabled

Bits 0, 2 – SSPnIE Synchronous Serial Port ‘n’ Interrupt Enable bit

ValueDescription
1 Enabled
0 Disabled
Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1-PIE8.