7.7.1 INTCON

Interrupt Control Register
Important: Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
Name: INTCON
Offset: 0x00B

Bit 76543210 
 GIEPEIE     INTEDG 
Access R/WR/WR/W 
Reset 001 

Bit 7 – GIE Global Interrupt Enable bit

ValueDescription
1 Enables all active interrupts
0 Disables all interrupts

Bit 6 – PEIE Peripheral Interrupt Enable bit

ValueDescription
1 Enables all active peripheral interrupts
0 Disables all peripheral interrupts

Bit 0 – INTEDG External Interrupt Edge Select bit

ValueDescription
1 Interrupt on rising edge of INT pin
0 Interrupt on falling edge of INT pin
Interrupt flag bits are set when an Interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit. User software must ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.