7.7.9 PIE7

Peripheral Interrupt Enable Register 7

Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1-PIE8.
Name: PIE7
Offset: 0x71D

Bit 76543210 
   NVMIENCO1IE  CWG2IECWG1IE 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 5 – NVMIE NVM Interrupt Enable bit

ValueDescription
1 Enabled
0 Disabled

Bit 4 – NCO1IE NCO Interrupt Enable bit

ValueDescription
1 Enabled
0 Disabled

Bit 1 – CWG2IE CWG2 Interrupt Enable bit

ValueDescription
1 Enabled
0 Disabled

Bit 0 – CWG1IE CWG1 Interrupt Enable bit

ValueDescription
1 Enabled
0 Disabled
Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1-PIE8.