7.7.6 PIE4

Peripheral Interrupt Enable Register 4

Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1-PIE8.
Name: PIE4
Offset: 0x71A

Bit 76543210 
   TMR6IETMR5IETMR4IETMR3IETMR2IETMR1IE 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 5 – TMR6IE TMR6 to PR6 Match Interrupt Enable bit

ValueDescription
1 Enabled
0 Disabled

Bit 4 – TMR5IE TMR5 Overflow Interrupt Enable bit

ValueDescription
1 Enabled
0 Disabled

Bit 3 – TMR4IE TMR4 to PR4 Match Interrupt Enable bit

ValueDescription
1 Enabled
0 Disabled

Bit 2 – TMR3IE TMR3 Overflow Interrupt Enable bit

ValueDescription
1 Enabled
0 Disabled

Bit 1 – TMR2IE TMR2 to PR2 Match Interrupt Enable bit

ValueDescription
1 Enabled
0 Disabled

Bit 0 – TMR1IE TMR1 Overflow Interrupt Enable bit

ValueDescription
1 Enabled
0 Disabled
Bit PEIE of the INTCON register must be set to enable any peripheral interrupt controlled by registers PIE1-PIE8.