7.7.8 PIE6
Peripheral Interrupt Enable Register 6
Note: Bit PEIE of the
INTCON register must be set to enable any peripheral interrupt
controlled by registers PIE1-PIE8.
Name: | PIE6 |
Offset: | 0x71C |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
CCP4IE | CCP3IE | CCP2IE | CCP1IE | ||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 0 |
Bit 3 – CCP4IE CCP4 Interrupt Enable bit
Value | Description |
---|---|
1 |
Enabled |
0 |
Disabled |
Bit 2 – CCP3IE CCP3 Interrupt Enable bit
Value | Description |
---|---|
1 |
Enabled |
0 |
Disabled |
Bit 1 – CCP2IE CCP2 Interrupt Enable bit
Value | Description |
---|---|
1 |
Enabled |
0 |
Disabled |
Bit 0 – CCP1IE CCP1 Interrupt Enable bit
Value | Description |
---|---|
1 |
Enabled |
0 |
Disabled |