16.3.9 DMA Channel x Destination
Address Register(1,2)
Note:
For SFR, the DMA module
operates over the entire address range.
For data space, the DMA
module operates over the entire range of available memory.
Table 16-11. Register Bit Attribute Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable
bit
HC
Cleared by
Hardware
(Gray
cell)
Unimplemented
W
Writable
bit
HS
Set by
Hardware
X
Bit is unknown
at Reset
C
Write to
clear
S
Software
settable bit
x
Channel
number
Name:
DMAxDST
Offset:
0x2320, 0x234C,
0x2378, 0x23A4, 0x23D0, 0x23FC
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
DADDR[23:16]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
DADDR[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
DADDR[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bits 23:0 – DADDR[23:0] Destination Address
bits
These bits indicate
the address location to which the DMA module initiates the write operation. DMAxDST
register is dynamically updated based on DAMODE[1:0] and RELOADD
bit.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
