16.3.7 DMA Channel x Status Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | DMAxSTAT |
| Offset: | 0x2318, 0x2344, 0x2370, 0x239C, 0x23C8, 0x23F4 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BWERR | BRERR | ||||||||
| Access | R/C/HS | R/C/HS | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ADRERR[1:0] | DONE | HALF | OVERRUN | MATCH | DBUFWF | ||||
| Access | R/C/HS | R/C/HS | R/C/HS | R/C/HS | R/C/HS | R/C/HS | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 9 – BWERR Bus Write Error Flag bit
| Value | Description |
|---|---|
| 1 | A bus write error has occurred; a write transaction could not be completed by the DMA |
| 0 | No bus write error has occurred |
Bit 8 – BRERR Bus Read Error Flag
| Value | Description |
|---|---|
| 1 | A bus read error has occurred |
| 0 | No bus read error has occurred |
Bits 7:6 – ADRERR[1:0] DMA Address Error Flag bits
| Value | Description |
|---|---|
| 11 | Address Fault due to the source/destination pointer being misaligned for the specified operation size |
| 10 | The DMA channel has attempted to access an address higher than DMAHIGH |
| 01 | The DMA channel has attempted to access an address lower than DMALOW, but above the SFR range |
| 00 | No DMA Fault condition |
Bit 5 – DONE DMA Complete Operation Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | The DMA channel’s DMAxCNT register has reached 0 |
| 0 | The DMA channel’s DMAxCNT register has not reached 0 |
Bit 4 – HALF DMA Halfway Watermark Level Interrupt Flag bit
| Value | Description |
|---|---|
| 1 | DMAxCNT register has reached the halfway point towards 0 |
| 0 | DMAxCNT register has not reached the halfway point towards 0 |
Bit 3 – OVERRUN DMA Channel Overrun Flag bit
| Value | Description |
|---|---|
| 1 | The DMA channel is triggered while it is still completing the operation based on the previous trigger |
| 0 | The overrun condition has not occurred |
Bit 1 – MATCH Pattern Match Status bit
| Value | Description |
|---|---|
| 1 | Pattern match has been detected |
| 0 | Pattern match has not been detected |
Bit 0 – DBUFWF Buffered Data Write Flag bit
| Value | Description |
|---|---|
| 1 | The content of the DMA buffer has not been written to the location specified in DMAxDST or DMAxSRC in Null Write mode |
| 0 | The content of the DMA buffer has been written to the location specified in DMAxDST or DMAxSRC in Null Write mode |