16.3.4 DMA High Address Limit Register

Note:

The HADDR[23:0] bits apply to data space only. SFR space outside the range from LADDR[23:0] to HADDR[23:0] is accessible by the DMA and will not result in an interrupt. Setting HADDR[23:0] to an address in SFR will, therefore, be ignored.

Table 16-6. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	DMAHIGH
Offset:	0x230C


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	HADDR[23:16]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	HADDR[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	HADDR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 23:0 – HADDR[23:0] High Limit Address bits⁽¹⁾

These bits specify the upper address limit. When the DMA module initiates a transaction beyond this limit, the associated channel interrupt occurs, ADRERR[1:0] is set to 10, and CHEN is cleared.

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