16.3.6 DMA Channel x Selection Register

Table 16-8. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	DMAxSEL
Offset:	0x2314, 0x2340, 0x236C, 0x2398, 0x23C4, 0x23F0


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	CHSEL[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 7:0 – CHSEL[7:0] DMA Channel Trigger Selection bits

These bits select one of the possible DMA triggers connected to the corresponding channel’s input. See DMA Trigger Sources for more DMA trigger source information.