16.3.1 DMA Module Control Register
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Gray cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| C | Write to clear | S | Software settable bit | x | Channel number |
| Name: | DMACON |
| Offset: | 0x2300 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ON | SIDL | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PRIORITY | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 15 – ON DMA Module Enable bit
| Value | Description |
|---|---|
| 1 | Enables DMA module |
| 0 | Disables module and terminates all active DMA operation(s) |
Bit 13 – SIDL DMA Stop in Idle bit
| Value | Description |
|---|---|
| 1 | Module stops operation when system enters Idle mode |
| 0 | Module continues operation when system enters Idle mode |
Bit 0 – PRIORITY Channel Priority Scheme Selection bit
| Value | Description |
|---|---|
| 1 | Round robin scheme |
| 0 | Fixed priority scheme |