27.4.4.1.1 Single Edge Compare Mode (High Output)

In this mode (see Figure 27-10), the output pin is initially driven low and remains low until a match occurs between the timer and CCPxRA register. The key timing events to note are:

• The output pin is driven high, one clock period after a match occurs between the Timer and CCPxRA registers. The output pin remains high until a mode change has been made or the module is disabled.
• The timer counts up until it rolls over or until the selected SYNC[4:0] input is asserted (depending on the value of SYNC[4:0]) and then resets to 0000h on the next clock.
• The compare interrupt signal (to set CCPxIF) is asserted, and the output pin is driven high.
• The timer interrupt signal (to set CCTxIF) is asserted for one clock period on a Time Base Reset or rollover event.