27.4.4.1.2 Single Compare Mode (Low Output)

Once the Compare mode has been enabled (Figure 27-11), the output pin will initially be driven high, and remain high until a match occurs between the timer and CCPxRA register. The key timing events to note are:

• The output pin is driven low one clock period after a match occurs between the timer and CCPxRA registers. The output pin remains low until a mode change has been made or the module is disabled.
• The timer counts up until it rolls over or until the selected SYNC[4:0] input is asserted, and then it resets to 0000h on the next clock.
• The compare interrupt signal (to set CCPxIF) is asserted and the output pin is driven low.
• The timer interrupt signal (to set CCTxIF) is asserted for one clock period on a Time Base Reset or rollover event.