27.4.4.1.3 Single Compare Mode (Toggled Output)
Once this Compare mode has been enabled (Figure 27-12), the output pin is initially driven low and then toggled on each subsequent match
event between the timer and CCPxRA register. The key timing events to note are:
- The state of the output pin is toggled one clock period after a match occurs between the timer and CCPxRA registers. The output pin remains at its new state until the next toggle event, until a mode change has been made or the module is disabled.
- The timer counts up until it rolls over, or until the selected SYNC[4:0] input is asserted, and then resets to 0000h on the next clock.
- The respective channel interrupt output (CCPxIF) is asserted when the output pin is toggled.
- The time base interrupt signal (CCTxIF) is generated on a Timer Reset or rollover event.
Note: The internal OCx pin output logic is set to a logic
‘
0’ on a device Reset; however, the initial output pin state for
the Toggle mode can be reversed using the POLACE polarity control bit.