6.6.8.8.3 Rounding Modes
The rounding mode for each instruction Functional Block is defined by the value written into FCR.RND [1:0]. The FPU treats the rounding mode input as an operand supplied from the RD-stage when the instruction is dispatched into the Execute stage.
FAND,
FIOR, FCPQ, FCPS,
FTST, FABS, FNEG,
FFLIM, FMAX, FMIN,
FMAXNUM, FMINNUM, FMOV,
FMOVC or any CPU to/from FPU data move instruction.There is a 3-bit rounding mode input (rnd [2:0]) to support up to eight different rounding modes for all FPU conversion operations. Setting rnd [2] = 1 and mapping rnd [1:0] to FCR [9:8] will allow user selection of the IEEE 754 compliant modes as defined in the FCR.
The integer/floating-point conversion instructions (FDI2F,
FLI2F, FF2DI, FF2LI) may either
specify the rounding mode within the instruction syntax or default to that defined in
FCR.RND [1:0]. The CPU will issue one of these instructions, and the FPU will use it to
determine the Functional Block Rounding mode as shown in Table 6-45.
| Rounding Mode Bits in Opcode[2:0] | Functional Block Rounding Mode |
|---|---|
111 | IEEE Round to Negative Infinity (floor) |
110 | IEEE Round to Positive Infinity (ceiling) |
101 | IEEE Round to Zero (truncate) |
100 | IEEE Round to Nearest (even) |
0xx | Global mode (defined by FCR.RND[1:0]) |