6.6.8.9 Floating-Point Status

The FPU generates four types of status:

  • Exception condition “most-recent” status from most instructions (see Table 6-48). These bits are located within FSR [6:0]:INX, HUGI, OVF, UDF, DIV0, INVAL, SUBO.
  • Exception condition "sticky" status from most instructions (see Table 6-48). These bits are located within FSR [14:8]: INXS, HUGIS, OVFS, UDFS, DIV0S, INVALS, SUBOS.
  • Value ordering relations status to indicate the result of the FCPS/FCPQ compare instructions. These bits are located within FSR [19:16]:GT, LT, EQ, UN.
  • Operand characteristic status from the FTST datum inspection/classify instruction. These bits are located within FSR [28:24]: SUB, INF, FZ, FN, FNAN.

Operand comparisons are likely to be used frequently, so the compare status bits generated by the FCPS/FCPQ instructions are supported with CPU conditional branch instructions. All other status must be read into the CPU (using the MOVCRW instruction) or pushed onto the stack (using PUSHCR) and then acted upon as necessary.

Note: Irrespective of whether an exception is masked or not, writing a logic 1 to an exception status flag using any instruction that can write 1’s to the FSR will not result in any associated exception being taken.