6.6.8.10 Generating FP Exceptions

The FPU can generate the five IEEE-754 2008 compliant exceptions. Each exception has a flag associated with it in the FSR register as noted below.

All instructions, except FTST, FMOV and FMOVC, can affect FSR exception status as a consequence of the operation (any exception status flag bits not set will be cleared). The FTST, FMOV and FMOVC instructions will neither set nor clear any exception flags. Refer to the IEEE-754 2008 standard for a more detailed definition.

“Most-recent” exception status only shows the exception status of the most recent instruction executed. It contains no accrued status from prior operations such that if a status bit is not affected or not signaled by the instruction, it will be cleared.

“Sticky” exception status contains accrued status from all instructions executed.

The following summarizes when exceptions are signaled, and the default results for each exception are summarized in Table 6-44. Refer to Table 6-47 for exception conditions and default results for each instruction.

  • Invalid: FSR.INVAL Exception signaled whenever an operation generates no usefully definable result. INVAL is set under the following conditions:
    • Any operation on a sNaN input
    • Addition of infinities with opposite signs, or subtraction of infinities with the same sign
    • Multiplication 0*infinity
    • Division 0/0 and infinity/infinity
    • Square root of a negative floating-point value
Note: INVAL is also set by FF2DI and FF2LI Float-to-Integer conversion instructions in the event of a qNaN or Infinity input value.
  • Divide by Zero: FSR.DIV0 Exception signaled whenever the FDIV instruction dividend is finite and the divisor is 0.
  • Overflow: FSR.OVF Exception signaled whenever an operation results in an overflow, defined as a post-rounded result that exceeds the largest finite number that the destination can represent.
  • Underflow: FSR.UDF Exception signaled whenever an operation results in a tiny but non-zero (subnormal) result (see Underflow with an Exact Rounded Result for a special case).
  • Inexact: FSR.INX Exception signaled whenever the rounded result of an operation is:
    • Not equal to the same result represented using infinite precision (i.e., has suffered a loss of accuracy)
    • Is subnormal and not an exact zero when FTZ mode is enabled

In addition, this macro also generates two additional exceptions:

  • Huge Integer: FSR.HUGI Exception signaled whenever a Float-to-Integer conversion operation (FF2DI and FF2LI) results in an integer value that is larger than the destination register can represent.
  • Subnormal Operand: FSR.SUBO Exception signaled whenever an operand of an affected instruction (see Subnormal Override Functions and Table   1) is a subnormal value, and Subnormals-Are-Zeros (SAZ) mode is disabled.