6.6.8.11.1 FP Status Access

The msws and lsws of the FSR are implemented as 16-bit registers which can be independently read and written by the CPU and FPU. This is intended to prevent structural hazards arising between FTST/FCPS/FCPQ/FBcc instructions (that access the FSR msw), and all other instructions that could affect the exception status (located in the FSR lsw). Hazards are not expected to exist between FTST and FCPS/FCPQ instructions.

The FCPS/FCPQ/FTST status located in msw of the FSR (FSRH) can be read and stacked by the PUSHCR instruction while the lsw of the FSR is written (or blocked to be written). The msws and lsws of the FSR are otherwise concatenated into a single 32-bit value (FSR) for read/write by the MOVCRW/MOVWCR and PUSHCR/POPCR instructions.

In addition, the FAND and FIOR instructions operate with a 16-bit literal and can be used to set or clear the bit in the FCR or lsw of the FSR or FEAR. When the FSR is referenced in these ops, users can manipulate the FPU exception status, but access to the FCPS/FCPQ/FTST status in FSRH is not possible. This choice assumes that the need to modify FTST/FCPS/FCPQ status is rare. Consequently, doing so using MOVCRW/MOVWCR or PUSHCR/POPCR is expected to be adequate.

Table 6-48. FP Instruction Status Operations
Instruction	FPU Status Register (FSR)
	FSR[28:24]					FSR[19:16]				FSR[14:8]							FSR[6:0]
	SUB	INF	FN	FZ	FNAN	GT	LT	EQ	UN	SUBOS	HUGIS	INXS	UDFS	OVFS	DIVOS	INVALS
Move Instructions
`FMOV`	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—
`FMOVC`	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—
Status Bit Set/Clear/Update Instructions
`FAND` ⁽¹⁾	—	—	—	—	—	—	—	—	—	⇓	⇓	⇓	⇓	⇓	⇓	⇓	⇓	⇓	⇓	⇓	⇓	⇓	⇓
`FIOR` ⁽¹⁾	—	—	—	—	—	—	—	—	—	⇑	⇑	⇑	⇑	⇑	⇑	⇑	⇑	⇑	⇑	⇑	⇑	⇑	⇑
`FTST`	⇕	⇕	⇕	⇕	⇕	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—	—
Conversion Instructions
`FLI2F`	—	—	—	—	—	—	—	—	—	—	—	⇑⁽²⁾	—	—	—	—	0	0	⇕⁽²⁾	0	0	0	0
`FDI2F`	—	—	—	—	—	—	—	—	—	—	—	⇑	—	—	—	—	0	0	⇕	0	0	0	0
`FF2LI`	—	—	—	—	—	—	—	—	—	⇑	⇑	⇑	—	—	—	⇑	⇕	⇕	⇕	0	0	0	⇕
`FF2DI`	—	—	—	—	—	—	—	—	—	⇑	⇑	⇑	—	—	—	⇑	⇕	⇕	⇕	0	0	0	⇕
Comparison Instructions
`FCPS`	—	—	—	—	—	⇕	⇕	⇕	⇕	⇑	—	—	—	—	—	⇑	⇕	0	0	0	0	0	⇕
`FCPQ`	—	—	—	—	—	⇕	⇕	⇕	⇕	⇑	—	—	—	—	—	⇑	⇕	0	0	0	0	0	⇕
`FFLIM`	—	—	—	—	—	—	—	—	—	⇑	—	—	—	—	—	⇑	⇕	0	0	0	0	0	⇕
`FMAX`	—	—	—	—	—	—	—	—	—	⇑	—	—	—	—	—	⇑	⇕	0	0	0	0	0	⇕
`FMAXNUM`	—	—	—	—	—	—	—	—	—	⇑	—	—	—	—	—	⇑	⇕	0	0	0	0	0	⇕
`FMIN`	—	—	—	—	—	—	—	—	—	⇑	—	—	—	—	—	⇑	⇕	0	0	0	0	0	⇕
`FMINNUM`	—	—	—	—	—	—	—	—	—	⇑	—	—	—	—	—	⇑	⇕	0	0	0	0	0	⇕
Math Instructions
`FADD`	—	—	—	—	—	—	—	—	—	⇑	—	⇑	⇑	⇑	—	⇑	⇕	0	⇕	⇕	⇕	0	⇕
`FSUB`	—	—	—	—	—	—	—	—	—	⇑	—	⇑	⇑	⇑	—	⇑	⇕	0	⇕	⇕	⇕	0	⇕
`FNEG`	—	—	—	—	—	—	—	—	—	⇑	—	—	—	—	—	—	⇕	—	—	—	—	—	—
`FABS`	—	—	—	—	—	—	—	—	—	⇑	—	—	—	—	—	—	⇕	—	—	—	—	—	—
`FMUL`	—	—	—	—	—	—	—	—	—	⇑	—	⇑	⇑	⇑	—	⇑	⇕	0	⇕	⇕	⇕	0	⇕
`FMAC`	—	—	—	—	—	—	—	—	—	⇑	—	⇑	⇑	⇑	—	⇑	⇕	0	⇕	⇕	⇕	0	⇕
`FDIV`	—	—	—	—	—	—	—	—	—	⇑	—	⇑	⇑	⇑	⇑	⇑	⇕	0	⇕	⇕	⇕	⇕	⇕
`FSQRT`	—	—	—	—	—	—	—	—	—	⇑	—	⇑	—	—	—	⇑	⇕	0	⇕	0	0	0	⇕
`FSIN`	—	—	—	—	—	—	—	—	—	⇑	—	⇑	⇑	—	—	⇑	⇕	0	⇕	⇕	0	0	⇕
`FCOS`	—	—	—	—	—	—	—	—	—	⇑	—	⇑	⇑	—	—	⇑	⇕	0	⇕	⇕	0	0	⇕
Key: ⇕ set or cleared, ‘0’ always cleared, — unchanged, ⇓ may be cleared but never set, ⇑ may be set but never cleared Note: With respect to the `FSR`, `FAND` and `FIOR` can only affect FSR[15:0] (exception status). When set, no exception is signaled. LI2F.s only. Inexact not possible for Long integer to Double Precision float (LI2F.d) conversion.