6.6.8.3.2 Floating-Point Unit Register Contexts

To speed up real time control systems and other time critical applications, the PIC32A FPU supports multiple register contexts that are tied to Interrupt Priority Levels.

The FPU includes a set of hardware register contexts. Each context includes the FSR, FCR and four register pairs (i.e., F0 through F7). All other F-regs and FEAR are not included and must be saved and restored through software.

The number of supported register contexts matches that of the CPU and is fixed at seven, which represents one context per CPU Interrupt Priority Level (IPL). Should the CPU change context, then the FPU will follow suit, and all subsequent instructions issued to the FPU will execute within that (new) context. However, all FPU instructions issued in a prior context will be allowed to continue to execute and retire within that context, irrespective of the context change within the CPU. Similarly, any data dependencies that occur within the context of the instruction underway will remain within that context.

As the FSR is part of the register context, exceptions are context specific. Should the FPU change register context, any FPU exceptions generated as a result of the execution of FPU instructions already issued from the prior context will remain pending until the FPU returns to that original context.

Hazard detection is also context-based such that each instruction operand and result register is tagged with its own context. Therefore, hazards can only exist within the same register context.

This concept extends to the FSR and FCR, which have independent representations within each register context. Consequently, the CPU will not stall (assuming no FSR and/or FCR hazard exists within the current context) if it accesses the FSR or FCR while the FPU continues to execute instructions issued from within a different context. These instructions will have access to their own version of the FSR and FCR.