6.6.8.9.2 Operand Characteristic (Test) Status

The FTST instruction will test the operand and update the SUB, INF, FN, FZ, FNAN status bits. No exceptions will be generated by this instruction. Due to the relative infrequent use of this instruction, dedicated conditional branches are not supported by the CPU to test these status bits. The user must read the FSR and then act upon the bits of instruction using existing CPU instructions.
Table 6-46. Floating-Point Conditional Branches and Associated Predicates
Assembler FBRA AttributeDesign Mnemonic CBRA MappingPredicatesAssembler FBRA AttributeDesign Mnemonic CBRA MappingNegated Predicates
Ordering

Relation

Definition(1)

(Alternative Definition)

Ordering

Relation

Definition(2)

(Alternative Definition)

><=?><=?
EQCBRA0FFTFEqualUNECBRA1TTFTUnordered or Greater Than or Less Than (Unordered or Not Equal)
NECBRA2TTFFGreater Than or Less Than (Not Equal)UEQ(3)CBRA3FFTTUnordered or Equal
GTCBRA4TFFFGreater ThanULECBRA5FTTTUnordered or Less Than or Equal
GECBRA6TFTFGreater Than or EqualULTCBRA7FTFTUnordered or Less Than
LTCBRA8FTFFLess ThanUGECBRA9TFTTUnordered or Greater Than or Equal
LECBRA10FTTFLess Than or EqualUGTCBRA11TFFTUnordered or Greater Than
ORCBRA12TTTFOrderedUNCBRA13FFFTUnordered