10.2.7.1.2 Configuring the Fusion Static PLL

The Fusion Static PLL includes an option to choose the source of the input clock as one of the following:

  • Hardwired I/O driven
  • External I/O driven
  • Core Logic driven
  • Crystal oscillator
  • RC oscillator

The option to bypass the PLL for the primary output.

Configuration selections available for frequency, delay and phase.

After you select the Static PLL from the Catalog, you must configure it. To do so:

  1. Select your output. A total of five outputs can be obtained from the Static PLL. Select the check box next to each required output to select it. The available outputs are:
    • GLA is always selected
    • GLB and YB have the same output frequency. They can be delayed by different amounts by setting the individual delays. GLB drives a Global while YB drives a core net. Using only YB also burns the global driver for GLB. However, the global rib is available.
    • GLC and YC have the same output frequency. They can be delayed by different amounts by setting the individual delays. GLB drives a Global while YB drives a core net. Using only YC also burns the global driver for GLB. However, the global rib is available.
    • The input signal CLKA is the reference clock for all five outputs
  2. Specify your Internal Feedback. The source of the feedback signals are the VCO output signal, with 0 degree phase shift and zero additional time delay. (top Selection on the Feedback MUX) or A delayed version of the VCO output, in selectable increments of 200 ps, up to 6.735 ns. This delay advances the feedback clock, thereby advancing all outputs by the delay value specified for the feedback delay element (middle selection of the Feedback MUX).
  3. Set your Fixed System Delay. By choosing the non-zero value for this delay, the feedback source signal can be further delayed by a fixed amount of mask delay designed to emulate the delay through the chip’s clock tree. This allows for clock-line de-skewing operations.
  4. Specify the following input clock settings:
    • Input Clock Frequency between 1.5 – 350 MHz
    • Input Clock Source as one of the following: Driven by the hardwired I/O; Driven by an external I/O from a different I/O location; Driven by Core Logic
  5. Specify the primary output beginning with the source of the input clock:
    • Output bypassing the PLL (top selection of the GLA MUX). In this case, VCO phase shift and output frequency selection are not available. Output frequency is the same as input frequency in this case.
    • Output directly from the VCO (middle selection of the GLA MUX). The phase shift of 0, 90, 180 or 270 is available in this case.
    • Delayed version of the zero phase shift output from the VCO. Phase-shift selection is unavailable for this (bottom selection of the GLA MUX). This output can be used for

      two purposes: a) to use the feedback delay as an additional delay on the output if feedback advance has not been specified (top and bottom selections of the feedback MUX); b) to compensate for the feedback advance for this particular output if feedback advance has been specified (middle selection of the feedback MUX).

    • Output frequency (1.5 – 350 MHz)
    • VCO Phase-Shift (one of 0, 90, 180 or 270 degrees); the phase shift is out of the VCO. The phase shift is impacted by the value of the divider after the VCO.
    • An optional Extra Output Delay, in selectable increments of 200 ps, up to 6.735 ns.
  6. Specify Secondary1 and Secondary2 Outputs. Select the source of the output clock:
    • Output directly from the VCO (top selection of the GLB/GLC MUX) - The phase shift of 0, 90, 180 or 270 is available in this case.
    • Delayed version of the zero phase shift output from the VCO - Phase-shift selection is unavailable for this (bottom selection of the GLB/GLC MUX). This output can be used for two purposes: a) to use the feedback delay as an additional delay on the output if feedback advance has not been specified (top and bottom selections of the feedback MUX); b) to compensate for the feedback advance for this particular output if feedback advance has been specified (middle selection of the feedback MUX).
    • Set your Output frequency (1.5 – 350 MHz)
    • VCO Phase-Shift (one of 0, 90, 180 or 270 degrees); the phase shift is out of the VCO. The phase shift is impacted by the value of the divider after the individual optional Extra Output Delay for each of the Global and Core outputs, in selectable increments of 200 ps, up to 6.735 ns.