23.1.1 CLCx Control Register Low
| Name: | CLCxCONL |
| Offset: | 0x0C4, 0x0D0, 0x0DC, 0x0E8 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LCEN | INTP | INTN | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LCOE | LCOUT | LCPOL | MODE[2:0] | ||||||
| Access | R/W | R | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bit 15 – LCEN CLCx Enable bit
| Value | Description |
|---|---|
| 1 | CLCx is enabled and mixing input signals |
| 0 | CLCx is disabled and has logic zero outputs |
Bit 11 – INTP CLCx Positive Edge Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt will be generated when a rising edge occurs on LCOUT |
| 0 | Interrupt will not be generated |
Bit 10 – INTN CLCx Negative Edge Interrupt Enable bit
| Value | Description |
|---|---|
| 1 | Interrupt will be generated when a falling edge occurs on LCOUT |
| 0 | Interrupt will not be generated |
Bit 7 – LCOE CLCx Port Enable bit
| Value | Description |
|---|---|
| 1 | CLCx port pin output is enabled |
| 0 | CLCx port pin output is disabled |
Bit 6 – LCOUT CLCx Data Output Status bit
| Value | Description |
|---|---|
| 1 | CLCx output high |
| 0 | CLCx output low |
Bit 5 – LCPOL CLCx Output Polarity Control bit
| Value | Description |
|---|---|
| 1 | The output of the module is inverted |
| 0 | The output of the module is not inverted |
Bits 2:0 – MODE[2:0] CLCx Mode bits
| Value | Description |
|---|---|
| 111 | Single input transparent latch with S and R |
| 110 | JK flip-flop with R |
| 101 | Two-input D flip-flop with R |
| 100 | Single input D flip-flop with S and R |
| 011 | SR latch |
| 010 | Four-input AND |
| 001 | Four-input OR-XOR |
| 000 | Four-input AND-OR |