23.1.4 CLCx Gate Logic Input Select Low Register
| Name: | CLCxGLSL |
| Offset: | 0x0C8, 0x0D4, 0x0E0, 0x0EC |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| G2D4T | G2D4N | G2D3T | G2D3N | G2D2T | G2D2N | G2D1T | G2D1N | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| G1D4T | G1D4N | G1D3T | G1D3N | G1D2T | G1D2N | G1D1T | G1D1N | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 15 – G2D4T Gate 2 Data Source 4 True Enable bit
| Value | Description |
|---|---|
| 1 | Data Source 4 signal is enabled for Gate 2 |
| 0 | Data Source 4 signal is disabled for Gate 2 |
Bit 14 – G2D4N Gate 2 Data Source 4 Negated Enable bit
| Value | Description |
|---|---|
| 1 | Data Source 4 inverted signal is enabled for Gate 2 |
| 0 | Data Source 4 inverted signal is disabled for Gate 2 |
Bit 13 – G2D3T Gate 2 Data Source 3 True Enable bit
| Value | Description |
|---|---|
| 1 | Data Source 3 signal is enabled for Gate 2 |
| 0 | Data Source 3 signal is disabled for Gate 2 |
Bit 12 – G2D3N Gate 2 Data Source 3 Negated Enable bit
| Value | Description |
|---|---|
| 1 | Data Source 3 inverted signal is enabled for Gate 2 |
| 0 | Data Source 3 inverted signal is disabled for Gate 2 |
Bit 11 – G2D2T Gate 2 Data Source 2 True Enable bit
| Value | Description |
|---|---|
| 1 | Data Source 2 signal is enabled for Gate 2 |
| 0 | Data Source 2 signal is disabled for Gate 2 |
Bit 10 – G2D2N Gate 2 Data Source 2 Negated Enable bit
| Value | Description |
|---|---|
| 1 | Data Source 2 inverted signal is enabled for Gate 2 |
| 0 | Data Source 2 inverted signal is disabled for Gate 2 |
Bit 9 – G2D1T Gate 2 Data Source 1 True Enable bit
| Value | Description |
|---|---|
| 1 | Data Source 1 signal is enabled for Gate 2 |
| 0 | Data Source 1 signal is disabled for Gate 2 |
Bit 8 – G2D1N Gate 2 Data Source 1 Negated Enable bit
| Value | Description |
|---|---|
| 1 | Data Source 1 inverted signal is enabled for Gate 2 |
| 0 | Data Source 1 inverted signal is disabled for Gate 2 |
Bit 7 – G1D4T Gate 1 Data Source 4 True Enable bit
| Value | Description |
|---|---|
| 1 | Data Source 4 signal is enabled for Gate 1 |
| 0 | Data Source 4 signal is disabled for Gate 1 |
Bit 6 – G1D4N Gate 1 Data Source 4 Negated Enable bit
| Value | Description |
|---|---|
| 1 | Data Source 4 inverted signal is enabled for Gate 1 |
| 0 | Data Source 4 inverted signal is disabled for Gate 1 |
Bit 5 – G1D3T Gate 1 Data Source 3 True Enable bit
| Value | Description |
|---|---|
| 1 | Data Source 3 signal is enabled for Gate 1 |
| 0 | Data Source 3 signal is disabled for Gate 1 |
Bit 4 – G1D3N Gate 1 Data Source 3 Negated Enable bit
| Value | Description |
|---|---|
| 1 | Data Source 3 inverted signal is enabled for Gate 1 |
| 0 | Data Source 3 inverted signal is disabled for Gate 1 |
Bit 3 – G1D2T Gate 1 Data Source 2 True Enable bit
| Value | Description |
|---|---|
| 1 | Data Source 2 signal is enabled for Gate 1 |
| 0 | Data Source 2 signal is disabled for Gate 1 |
Bit 2 – G1D2N Gate 1 Data Source 2 Negated Enable bit
| Value | Description |
|---|---|
| 1 | Data Source 2 inverted signal is enabled for Gate 1 |
| 0 | Data Source 2 inverted signal is disabled for Gate 1 |
Bit 1 – G1D1T Gate 1 Data Source 1 True Enable bit
| Value | Description |
|---|---|
| 1 | Data Source 1 signal is enabled for Gate 1 |
| 0 | Data Source 1 signal is disabled for Gate 1 |
Bit 0 – G1D1N Gate 1 Data Source 1 Negated Enable bit
| Value | Description |
|---|---|
| 1 | Data Source 1 inverted signal is enabled for Gate 1 |
| 0 | Data Source 1 inverted signal is disabled for Gate 1 |