23.1.5 CLCx Gate Logic Input Select High Register
| Name: | CLCxGLSH |
| Offset: | 0x0CA, 0x0D6, 0x0E2, 0x0EE |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| G4D4T | G4D4N | G4D3T | G4D3N | G4D2T | G4D2N | G4D1T | G4D1N | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| G3D4T | G3D4N | G3D3T | G3D3N | G3D2T | G3D2N | G3D1T | G3D1N | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 15 – G4D4T Gate 4 Data Source 4 True Enable bit
| Value | Description |
|---|---|
| 1 |
Data Source 4 signal is enabled for Gate 4 |
| 0 |
Data Source 4 signal is disabled for Gate 4 |
Bit 14 – G4D4N Gate 4 Data Source 4 Negated Enable bit
| Value | Description |
|---|---|
| 1 |
Data Source 4 inverted signal is enabled for Gate 4 |
| 0 |
Data Source 4 inverted signal is disabled for Gate 4 |
Bit 13 – G4D3T Gate 4 Data Source 3 True Enable bit
| Value | Description |
|---|---|
| 1 |
Data Source 3 signal is enabled for Gate 4 |
| 0 |
Data Source 3 signal is disabled for Gate 4 |
Bit 12 – G4D3N Gate 4 Data Source 3 Negated Enable bit
| Value | Description |
|---|---|
| 1 |
Data Source 3 inverted signal is enabled for Gate 4 |
| 0 |
Data Source 3 inverted signal is disabled for Gate 4 |
Bit 11 – G4D2T Gate 4 Data Source 2 True Enable bit
| Value | Description |
|---|---|
| 1 |
Data Source 2 signal is enabled for Gate 4 |
| 0 |
Data Source 2 signal is disabled for Gate 4 |
Bit 10 – G4D2N Gate 4 Data Source 2 Negated Enable bit
| Value | Description |
|---|---|
| 1 |
Data Source 2 inverted signal is enabled for Gate 4 |
| 0 |
Data Source 2 inverted signal is disabled for Gate 4 |
Bit 9 – G4D1T Gate 4 Data Source 1 True Enable bit
| Value | Description |
|---|---|
| 1 |
Data Source 1 signal is enabled for Gate 4 |
| 0 |
Data Source 1 signal is disabled for Gate 4 |
Bit 8 – G4D1N Gate 4 Data Source 1 Negated Enable bit
| Value | Description |
|---|---|
| 1 |
Data Source 1 inverted signal is enabled for Gate 4 |
| 0 |
Data Source 1 inverted signal is disabled for Gate 4 |
Bit 7 – G3D4T Gate 3 Data Source 4 True Enable bit
| Value | Description |
|---|---|
| 1 |
Data Source 4 signal is enabled for Gate 3 |
| 0 |
Data Source 4 signal is disabled for Gate 3 |
Bit 6 – G3D4N Gate 3 Data Source 4 Negated Enable bit
| Value | Description |
|---|---|
| 1 |
Data Source 4 inverted signal is enabled for Gate 3 |
| 0 |
Data Source 4 inverted signal is disabled for Gate 3 |
Bit 5 – G3D3T Gate 3 Data Source 3 True Enable bit
| Value | Description |
|---|---|
| 1 |
Data Source 3 signal is enabled for Gate 3 |
| 0 |
Data Source 3 signal is disabled for Gate 3 |
Bit 4 – G3D3N Gate 3 Data Source 3 Negated Enable bit
| Value | Description |
|---|---|
| 1 |
Data Source 3 inverted signal is enabled for Gate 3 |
| 0 |
Data Source 3 inverted signal is disabled for Gate 3 |
Bit 3 – G3D2T Gate 3 Data Source 2 True Enable bit
| Value | Description |
|---|---|
| 1 |
Data Source 2 signal is enabled for Gate 3 |
| 0 |
Data Source 2 signal is disabled for Gate 3 |
Bit 2 – G3D2N Gate 3 Data Source 2 Negated Enable bit
| Value | Description |
|---|---|
| 1 |
Data Source 2 inverted signal is enabled for Gate 3 |
| 0 |
Data Source 2 inverted signal is disabled for Gate 3 |
Bit 1 – G3D1T Gate 3 Data Source 1 True Enable bit
| Value | Description |
|---|---|
| 1 |
Data Source 1 signal is enabled for Gate 3 |
| 0 |
Data Source 1 signal is disabled for Gate 3 |
Bit 0 – G3D1N Gate 3 Data Source 1 Negated Enable bit
| Value | Description |
|---|---|
| 1 |
Data Source 1 inverted signal is enabled for Gate 3 |
| 0 |
Data Source 1 inverted signal is disabled for Gate 3 |