23.1.3 CLCx Input MUX Select Register

Name:	CLCxSEL
Offset:	0x0C8, 0x0D4, 0x0E0, 0x0EC


Bit	15	14	13	12	11	10	9	8
		DS4[2:0]				DS3[2:0]
Access		R/W	R/W	R/W		R/W	R/W	R/W
Reset		0	0	0		0	0	0


Bit	7	6	5	4	3	2	1	0
		DS2[2:0]				DS1[2:0]
Access		R/W	R/W	R/W		R/W	R/W	R/W
Reset		0	0	0		0	0	0

Bits 14:12 – DS4[2:0] Data Selection MUX 4 Signal Selection bits

Value	Description
111	SCCP3 auxiliary out
110	SCCP1 auxiliary out
101	CLCIND RP pin
100	Reserved
011	SPI1 Input (SDIx)
010	Comparator 3 out
001	CLC2 output
000	PWM Event A

Bits 10:8 – DS3[2:0] Data Selection MUX 3 Signal Selection bits

Value	Description
111	SCCP4 OC out
110	SCCP3 OC out
101	CLC4 out
100	UART1 RX
011	SPI1 Output (SDOx)
010	Comparator 2 output
001	CLC1 output
000	CLCINC I/O pin

Bits 6:4 – DS2[2:0] Data Selection MUX 2 Signal Selection bits

Value	Description
111	SCCP2 OC out
110	SCCP1 OC out
101	Comparator 6 output
100	Comparator 5 output
011	UART1 TX
010	Comparator 1 output
001	Comparator 4 Output
000	CLCINB I/O pin

Bits 2:0 – DS1[2:0] Data Selection MUX 1 Signal Selection bits

Value	Description
111	SCCP4 auxiliary out
110	SCCP2 auxiliary out
101	Reserved
100	REFCLKO output
011	INTRC/LPRC clock source
010	CLC3 out
001	System clock (F_CY)
000	CLCINA I/O pin

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