9.3 Input Change Notification (ICN)
The Input Change Notification function of the I/O ports allows the dsPIC33CK512MPT608 family devices to generate interrupt requests to the processor in response to a Change-of-State (COS) on selected input pins. This feature can detect input Change-of-States, even in Sleep mode, when the clocks are disabled. Every I/O port pin can be selected (enabled) for generating an interrupt request on a Change-of-State. Five control registers are associated with the Change Notification (CN) functionality of each I/O port. To enable the Change Notification feature for the port, the ON bit (CNCONx[15]) must be set.
The CNEN0x and CNEN1x registers contain the CN interrupt enable control bits for each of the input pins. The setting of these bits enables a CN interrupt for the corresponding pins. Also, these bits, in combination with the CNSTYLE bit (CNCONx[11]), define a type of transition when the interrupt is generated. Possible CN event options are listed in Table 1.
| CNSTYLE Bit (CNCONx[11]) | CNEN1x Bit | CNEN0x Bit | Change Notification Event Description |
|---|---|---|---|
0 | Does not matter | 0 | Disabled |
0 | Does not matter | 1 | Detects a mismatch between the last read state and the current state of the pin |
1 | 0 | 0 | Disabled |
1 | 0 | 1 | Detects a positive transition only
(from ‘0’ to ‘1’) |
1 | 1 | 0 | Detects a negative transition only
(from ‘1’ to ‘0’) |
1 | 1 | 1 | Detects both positive and negative transitions |
The CNSTATx register indicates whether a change occurred on the corresponding pin since the last read of the PORTx bit. In addition to the CNSTATx register, the CNFx register is implemented for each port. This register contains flags for Change Notification events. These flags are set if the valid transition edge, selected in the CNEN0x and CNEN1x registers, is detected. CNFx stores the occurrence of the event. CNFx bits must be cleared in software to get the next Change Notification interrupt. The CN interrupt is generated only for the I/Os configured as inputs (corresponding TRISx bits must be set).