9.9 Mapping Limitations
The control schema of the peripheral select pins is not limited to a small range of fixed peripheral configurations. There are no mutual or hardware-enforced lockouts between any of the peripheral mapping SFRs. Literally, any combination of peripheral mappings, across any or all of the RPn pins, is possible. This includes both many-to-one and one-to-many mappings of peripheral inputs, and outputs to pins. While such mappings may be technically possible from a configuration point of view, they may not be supportable from an electrical point of view (see Table 9-5).
| Register | RP Pin | I/O Port |
|---|---|---|
| RPOR0[5:0] | RP32 | Port Pin RB0 |
| RPOR0[13:8] | RP33 | Port Pin RB1 |
| RPOR1[5:0] | RP34 | Port Pin RB2 |
| RPOR1[13:8] | RP35 | Port Pin RB3 |
| RPOR2[5:0] | RP36 | Port Pin RB4 |
| RPOR2[13:8] | RP37 | Port Pin RB5 |
| RPOR3[5:0] | RP38 | Port Pin RB6 |
| RPOR3[13:8] | RP39 | Port Pin RB7 |
| RPOR4[5:0] | RP40 | Port Pin RB8 |
| RPOR4[13:8] | RP41 | Port Pin RB9 |
| RPOR5[5:0] | RP42 | Port Pin RB10 |
| RPOR5[13:8] | RP43 | Port Pin RB11 |
| RPOR6[5:0] | RP44 | Port Pin RB12 |
| RPOR6[13:8] | RP45 | Port Pin RB13 |
| RPOR7[5:0] | RP46 | Port Pin RB14 |
| RPOR7[13:8] | RP47 | Port Pin RB15 |
| RPOR8[5:0] | RP48 | Port Pin RC0 |
| RPOR8[13:8] | RP49 | Port Pin RC1 |
| RPOR9[5:0] | RP50 | Port Pin RC2 |
| RPOR9[13:8] | RP51 | Port Pin RC3 |
| Reserved | RP52-RP53 | Reserved |
| RPOR11[5:0] | RP54 | Port Pin RC6 |
| RPOR11[13:8] | RP55 | Port Pin RC7 |
| RPOR12[5:0] | RP56 | Port Pin RC8 |
| RPOR12[13:8] | RP57 | Port Pin RC9 |
| Reserved | RP58-RP59 | Reserved |
| RPOR14[5:0] | RP60 | Port Pin RC12 |
| RPOR14[13:8] | RP61 | Port Pin RC13 |
| RPOR15[5:0] | RP62 | Port Pin RC14 |
| RPOR15[13:8] | RP63 | Port Pin RC15 |
| RPOR16[5:0] | RP64 | Port Pin RD0 |
| RPOR16[13:8] | RP65 | Port Pin RD1 |
| RPOR17[5:0] | RP66 | Port Pin RD2 |
| Reserved | RP67-RP68 | Reserved |
| RPOR18[13:8] | RP69 | Port Pin RD5 |
| RPOR19[5:0] | RP70 | Port Pin RD6 |
| RPOR19[13:8] | RP71 | Port Pin RD7 |
| RPOR20[5:0] | RP72 | Port Pin RD8 |
| RPOR20[13:8] | RP73 | Port Pin RD9 |
| RPOR21[5:0] | RP74 | Port Pin RD10 |
| RPOR21[13:8] | RP75 | Port Pin RD11 |
| RPOR22[5:0] | RP76 | Port Pin RD12 |
| RPOR22[13:8] | RP77 | Port Pin RD13 |
| RPOR23[5:0] | RP78 | Port Pin RD14 |
| RPOR23[13:8] | RP79 | Port Pin RD15 |
| Reserved | RP80-RP175 | Reserved |
| RPOR34[5:0] | RP176 | Virtual Pin RPV0 |
| RPOR34[13:8] | RP177 | Virtual Pin RPV1 |
| RPOR35[5:0] | RP178 | Virtual Pin RPV2 |
| RPOR35[13:8] | RP179 | Virtual Pin RPV3 |
| RPOR36[5:0] | RP180 | Virtual Pin RPV4 |
| RPOR36[13:8] | RP181 | Virtual Pin RPV5 |
|
Note:
| ||
| Function | RPnR[5:0] | Output Name |
|---|---|---|
| Default Port | 0 | RPn tied to Default Pin |
| U1TX | 1 | RPn tied to UART1 Transmit |
| U1RTS | 2 | RPn tied to UART1 Request-to-Send |
| U2TX | 3 | RPn tied to UART2 Transmit |
| U2RTS | 4 | RPn tied to UART2 Request-to-Send |
| SDO1 | 5 | RPn tied to SPI1 Data Output |
| SCK1 | 6 | RPn tied to SPI1 Clock Output |
| SS1 | 7 | RPn tied to SPI1 Client Select |
| SDO2 | 8 | RPn tied to SPI2 Data Output |
| SCK2 | 9 | RPn tied to SPI2 Clock Output |
| SS2 | 10 | RPn tied to SPI2 Client Select |
| SD03 | 11 | RPn tied to SPI3 Data Output |
| SCK3 | 12 | RPn tied to SPI3 Clock output |
| SS3 | 13 | RPn tied to SPI3 Client Select |
| REFCLKO | 14 | RPn tied to Reference Clock Output |
| OCM1 | 15 | RPn tied to SCCP1 Output |
| OCM2 | 16 | RPn tied to SCCP2 Output |
| OCM3 | 17 | RPn tied to SCCP3 Output |
| OCM4 | 18 | RPn tied to SCCP4 Output |
| OCM5 | 19 | RPn tied to SCCP5 Output |
| OCM6 | 20 | RPn tied to SCCP6 Output |
| CAN1 | 21 | RPn tied to CAN1 Output |
| CAN2 | 22 | RPn tied to CAN2 Output |
| CMP1 | 23 | RPn tied to Comparator 1 Output |
| CMP2 | 24 | RPn tied to Comparator 2 Output |
| CMP3 | 25 | RPn tied to Comparator 3 Output |
| CMP4 | 26 | RPn tied to Comparator 4 Output |
| U3TX | 27 | RPn tied to UART3 Transmit |
| U3RTS | 28 | RPn tied to UART3 Request-to-Send |
| CMP5 | 32 | RPn tied to Comparator 5 Output |
| CMP6 | 33 | RPn tied to Comparator 6 Output |
| PWM4H | 34 | RPn tied to PWM4H Output |
| PWM4L | 35 | RPn tied to PWM4L Output |
| PWMEA | 36 | RPn tied to PWM Event A Output |
| PWMEB | 37 | RPn tied to PWM Event B Output |
| QEICMP1 | 38 | RPn tied to QEI1 Comparator Output |
| QEICMP2 | 39 | RPn tied to QEI2 Comparator Output |
| CLC1OUT | 40 | RPn tied to CLC1 Output |
| CLC2OUT | 41 | RPn tied to CLC2 Output |
| OCM7 | 42 | RPn tied to SCCP7 Output |
| OCM8 | 43 | RPn tied to SCCP8 Output |
| PWMEC | 44 | RPn tied to PWM Event C Output |
| PWMED | 45 | RPn tied to PWM Event D Output |
| PTGTRG24 | 46 | PTG Trigger Output 24 |
| PTGTRG25 | 47 | PTG Trigger Output 25 |
| SENT1OUT | 48 | RPn tied to SENT1 Output |
| SENT2OUT | 49 | RPn tied to SENT2 Output |
| MCCP9A | 50 | RPn tied to MCCP9 Output A |
| MCCP9B | 51 | RPn tied to MCCP9 Output B |
| MCCP9C | 52 | RPn tied to MCCP9 Output C |
| MCCP9D | 53 | RPn tied to MCCP9 Output D |
| MCCP9E | 54 | RPn tied to MCCP9 Output E |
| MCCP9F | 55 | RPn tied to MCCP9 Output F |
| QEICMP3 | 58 | RPn tied to QEI3 Comparator Output |
| CLC3OUT | 59 | RPn tied to CLC3 Output |
| CLC4OUT | 60 | RPn tied to CLC4 Output |
| U1DTR | 61 | RPn tied to UART1 DTR |
| U2DTR | 62 | RPn tied to UART2 DTR |
| U3DTR | 63 | RPn tied to UART3 DTR |
|
Note:
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