30.7.1 Watchdog Timer Control Register Low

Note:
  1. A read of this bit will result in a ‘1’ if the WDT is enabled by the device configuration or by software. The user’s software should not read or write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
  2. The user’s software should not read or write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
  3. These bits reflect the value of the Configuration bits.
  4. The WDTWINEN bit reflects the status of the Configuration bit if the bit is set. If the bit is cleared, the value is controlled by software.
  5. The available clock sources are device-dependent.

Legend: y = Value from Configuration bit on POR, HS = Hardware Settable bit

Name: WDTCONL
Offset: 0xFB4

Bit 15141312111098 
 ON  RUNDIV[4:0] 
Access R/WRRRRR 
Reset 00000y 
Bit 76543210 
 CLKSEL[1:0]SLPDIV[4:0]WDTWINEN 
Access RRRRRRRHS/R/W 
Reset 0000y0 

Bit 15 – ON  Watchdog Timer Enable bit(1,2)

ValueDescription
1

Enables the Watchdog Timer if it is not enabled by the device configuration
0

Disables the Watchdog Timer if it was enabled in software

Bits 12:8 – RUNDIV[4:0]  WDT Run Mode Postscaler Status bits(3)

ValueDescription
11111

Divide by 2 ^ 31 = 2,147,483,648
11110

Divide by 2 ^ 30 = 1,073,741,824
. . .
00001

Divide by 2 ^ 1, 2
00000

Divide by 2 ^ 0, 1

Bits 7:6 – CLKSEL[1:0]  WDT Run Mode Clock Select Status bits(3,5)

ValueDescription
11 LPRC Oscillator
10 FRC Oscillator
01 Reserved
00 SYSCLK

Bits 5:1 – SLPDIV[4:0]  Sleep and Idle Mode WDT Postscaler Status bits(3)

ValueDescription
11111

Divide by 2 ^ 31 = 2,147,483,648
11110

Divide by 2 ^ 30 = 1,073,741,824
. . .
00001

Divide by 2 ^ 1, 2
00000

Divide by 2 ^ 0, 1

Bit 0 – WDTWINEN  Watchdog Timer Window Enable bit(4)

ValueDescription
1

Enables Window mode
0

Disables Window mode