10.1 Primary PLL

The Primary Oscillator and internal FRC Oscillator sources can optionally use an on-chip PLL to obtain higher operating speeds. Figure 10-3 illustrates a block diagram of the Primary PLL module.

For PLL operation, the following requirements must be met at all times without exception:

• The PLL Input Frequency (F_PLLI) must be in the range of 8 MHz to 64 MHz
• The PFD Input Frequency (F_PFD) must be in the range of 8 MHz to (F_VCO/16) MHz

The VCO Output Frequency (F_VCO) must be in the range of 400 MHz to 1600 MHz

Equation 10-1 provides the relationship between the PLL Input Frequency (F_PLLI) and VCO Output Frequency (F_VCO).

Equation 10-2 provides the relationship between the PLL Input Frequency (F_PLLI) and PLL Output Frequency (F_PLLO).

Note: The PLL Phase Detector Input Divider Select (PLLPREx) bits and the PLL Feedback Divider (PLLFBDIVx) bits should not be changed when operating in PLL mode. Therefore, the user must start on either a non-PLL source or clock switch to a non-PLL source (e.g., internal FRC Oscillator) to make any necessary changes and then clock switch to the desired PLL source.

Using Two-Speed Start-up (IESO (FOSCSEL[7])) with a PLL source will start the device on the FRC while preparing the PLL. Once the PLL is ready, the device will switch automatically to the new source. This mode should not be used if changes are needed to the PLLPREx and PLLFBDIVx bits because the PLL may be running before user code execution begins.

It is not permitted to directly clock switch from one PLL clock source to a different PLL clock source. The user would need to transition between PLL clock sources with a clock switch to a non-PLL clock source.

//code example for 50 MIPS system clock using 8MHz FRC
// Select Internal FRC at POR
_FOSCSEL(FNOSC_FRC & IESO_OFF);
// Enable Clock Switching
_FOSC(FCKSM_CSECMD);
int main()
{
// Configure PLL prescaler, both PLL postscalers, and PLL feedback divider
CLKDIVbits.PLLPRE = 1;         // N1=1
PLLFBDbits.PLLFBDIV = 125;     // M = 125
PLLDIVbits.POST1DIV = 5;       // N2=5
PLLDIVbits.POST2DIV = 1;       // N3=1
// Initiate Clock Switch to FRC with PLL (NOSC=0b001)
__builtin_write_OSCCONH(0x01);
__builtin_write_OSCCONL(OSCCON | 0x01);
// Wait for Clock switch to occur
while (OSCCONbits.OSWEN!= 0);
}