10.2 Auxiliary PLL

The dsPIC33CK512MPT608 device family implements an Auxiliary PLL (APLL) module for each core present. The APLL is used to generate various peripheral clock sources independent of the system clock. Figure 10-4 shows a block diagram of the Auxiliary core APLL module.

For APLL operation, the following requirements must be met at all times without exception:

• The APLL Input Frequency (AF_PLLI) must be in the range of 8 MHz to 64 MHz
• The APFD Input Frequency (AF_PFD) must be in the range of 8 MHz to (AF_VCO/16) MHz
• The AVCO Output Frequency (AF_VCO) must be in the range of 400 MHz to 1600 MHz

Equation 10-3 provides the relationship between the APLL Input Frequency (AF_PLLI) and the AVCO Output Frequency (AF_VCO).

Equation 10-4 provides the relationship between the APLL Input Frequency (AF_PLLI) and APLL Output Frequency (AF_PLLO).

Where:

M = APLLFBDIV[7:0]

N1 = APLLPRE[3:0]

N2 = APOST1DIV[2:0]

N3 = APOST2DIV[2:0]

//code example for AFVCO = 1 GHz and AFPLLO = 500 MHz using 8 MHz internal FRC
// Configure the source clock for the APLL
ACLKCON1bits.FRCSEL = 1;       // Select internal FRC as the clock source
// Configure the APLL prescaler, APLL feedback divider, and both APLL postscalers.
ACLKCON1bits.APLLPRE = 1;      // N1 = 1
APLLFBD1bits.APLLFBDIV = 125;  // M = 125
APLLDIV1bits.APOST1DIV = 2;    // N2 = 2
APLLDIV1bits.APOST2DIV = 1;    // N3 = 1
// Enable APLL
ACLKCON1bits.APLLEN = 1;