10.3 CPU Clocking

The dsPIC33CK512MPT608 devices can be configured to use any of the following clock configurations:

  • Primary Oscillator (POSC) on the OSCI and OSCO pins
  • Internal Fast RC (FRC) Oscillator with optional clock divider
  • Internal Low-Power RC Oscillator
  • Primary Oscillator with PLL (ECPLL, HSPLL, XTPLL)
  • Internal Fast RC Oscillator with PLL (FRCPLL)
  • Backup Internal Fast RC Oscillator (BFRC)

The system clock source is divided by two to produce the internal instruction cycle clock. In this document, the instruction cycle clock is denoted by FCY. The timing diagram in Figure 10-5 illustrates the relationship between the system clock (FOSC), the instruction cycle clock (FCY) and the Program Counter (PC).

The internal instruction cycle clock (FCY) can be output on the OSCO I/O pin if the Primary Oscillator mode (POSCMD[1:0]) is not configured as HS/XT. For more information, see Oscillator with High-Frequency PLL.

Figure 10-5. Clock and Instruction Cycle Timing