4.3.2.1 Fault Simulation

A mechanism is available to simulate a BIST failure to allow testing of Fault handling software. When the FLTINJ bit is set during a run-time BIST, the MBISTSTAT bit will be set regardless of the test result. The procedure for a BIST Fault simulation is as follows:

  1. Execute the unlock sequence by consecutively writing 0x55 and 0xAA to the NVMKEY register.
  2. Set the MBISTEN bit (MBISTCON[0]).
  3. Execute 2nd unlock sequence by consecutively writing 0x55 and 0xAA to the NVMKEY register.
  4. Set the FLTINJ bit (MBISTCON[8]).
  5. Execute a Software Reset command.
  6. Verify a Software Reset has occurred by reading SWR (RCON[6]) (optional).
  7. Verify the MBISTDONE, MBSITSTAT and FLTINJ bits are all set.