4.3.3 MBIST Control Register
Note:
- Resets only on a true POR Reset.
- This bit will self-clear when the MBIST test is complete.
Legend: HS = Hardware Settable bit; HC = Hardware Clearable bit
Name: | MBISTCON |
Offset: | 0EFC |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
FLTINJ | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
MBISTDONE | MBISTSTAT | MBISTEN | |||||||
Access | R/W/HS | R | R/W/HC | ||||||
Reset | 0 | 0 | 0 |
Bit 8 – FLTINJ MBIST Fault Inject Control bit(1)
Value | Description |
---|---|
1 | The
MBIST test will complete and sets MBISTSTAT = 1 , simulating
an SRAM test failure |
0 | The MBIST test will execute normally |
Bit 7 – MBISTDONE MBIST Done Status bit
Value | Description |
---|---|
1 |
An MBIST operation has been executed |
0 | No MBIST operation has occurred on the last Reset sequence |
Bit 4 – MBISTSTAT MBIST Status bit
Value | Description |
---|---|
1 |
The last MBIST failed |
0 | The last MBIST passed; all memory may not have been tested |
Bit 0 – MBISTEN MBIST Enable bit(2)
Value | Description |
---|---|
1 |
MBIST test is armed; an MBIST test will execute at the next device Reset |
0 | MBIST test is disarmed |