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Digital Signal Controllers with Secure Subsystem

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11 Direct Memory Access (DMA) Controller
11.2 Typical Setup
11.2.1 Peripheral Module Disable

Description
Operating Conditions
Core: dsPIC33CK CPU
Advanced Flash Features
Security Features
Safety Features
Clock Management
Power Management
High-Resolution PWM with Fine Edge Placement
Timers/Output Compare/Input Capture
Advanced Analog Features
Communication Interfaces
Direct Memory Access (DMA)
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Pin Diagram
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Terminology Cross Reference
1 Device Overview
2 Guidelines for Getting Started with Digital Signal Controllers
3 CPU
4 Memory Organization
5 Flash Program Memory
6 Secure Subsystem
7 Resets
8 Interrupt Controller
9 I/O Ports
10 Oscillator with High-Frequency PLL
11 Direct Memory Access (DMA) Controller
- 11.1 Summary of DMA Operations
- 11.2 Typical Setup
12 Controller Area Network Flexible Data-Rate (CAN FD) Modules
13 High-Resolution PWM with Fine Edge Placement
14 High-Speed, 12-Bit Analog-to-Digital Converter
15 High-Speed Analog Comparator with Slope Compensation DAC
16 Quadrature Encoder Interface (QEI)
17 Universal Asynchronous Receiver Transmitter (UART)
18 Serial Peripheral Interface (SPI)
19 Inter-Integrated Circuit (I²C)
20 Single-Edge Nibble Transmission (SENT)
21 Timer1
22 Capture/Compare/PWM/Timer Modules (SCCP)
23 Configurable Logic Cell (CLC)
24 Peripheral Trigger Generator (PTG)
25 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator
26 Current Bias Generator (CBG)
27 Operational Amplifier
28 Deadman Timer (DMT)
29 Power-Saving Features
30 Special Features
31 Instruction Set Summary
32 Development Support
33 Electrical Characteristics
34 Packaging Information
35 Revision History
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11.2.1 Peripheral Module Disable

The channels of the DMA Controller can be individually powered down using the Peripheral Module Disable (PMD) registers.

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