11.2.3 DMA Control Registers


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00 ... 0x0AA7	Reserved
0x0AA8	DMACON	15:8	DMAEN		DMASIDL
0x0AA8	DMACON	7:0								PRSSEL
0x0AAA ... 0x0AAF	Reserved
0x0AB0	DMACHn	15:8				Reserved		NULLW	RELOAD	CHREQ
0x0AB0	DMACHn	7:0	SAMODE[1:0]		DAMODE[1:0]		TRMODE[1:0]		SIZE	CHEN
0x0AB2	DMAINTn	15:8	DBUFWF	CHSEL[6:0]
0x0AB2	DMAINTn	7:0	HIGHIF	LOWIF	DONEIF	HALFIF	OVRUNIF			HALFEN

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