11.2.2 DMA Registers

The DMA Controller uses a number of registers to control its operation. The number of registers depends on the number of channels implemented for a particular device.

There are always four module-level registers (one control and three buffer/address):

• DMACON: DMA Engine Control Register (DMACON)
• DMAH and DMAL: DMA High and Low Address Limit Registers
• DMABUF: DMA Transfer Data Buffer

Each of the DMA channels implements five registers (two control and three buffer/address):

• DMACHn: DMA Channel n Control Register (DMACHn)
• DMAINTn: DMA Channel n Interrupt Register (DMAINTn)
• DMASRCn: DMA Data Source Address Pointer for Channel n Register
• DMADSTn: DMA Data Destination Source for Channel n Register
• DMACNTn: DMA Transaction Counter for 
Channel n Register

For devices, there are a total of 34 registers.