2.6.39 LDO1 HIBERNATE Mode Status
| Name: | LDO1-HIB |
| Address: | 0x52 |
| Default: | 0b00 (VSETL1 pin definition) |
| Property: | R/W |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EN | Reserved | VSET[5:0] | |||||||
| Access | R/W | R | R/W | R/W | R/W | R/W | R/W | R/W | |
| Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – EN Enable bit of the HIBERNATE Mode Status
Bit 6 – Reserved
Bits 5:0 – VSET[5:0] Output voltage selection bits for the HIBERNATE Mode Status
Its default value is defined by the resistor at the VSETL1 pin during power-on start.
