2.6.4 System Timing Settings

Name:	SYS-TMG
Address:	0x02
Default:	0x12
Property:	R/W


Bit	7	6	5	4	3	2	1	0
	ENTO[1:0]		ENINTTO[1:0]		Reserved	RSTDLY[2:0]
Access	R/W	R/W	R/W	R/W	R	R/W	R/W	R/W
Default	0	0	0	1	0	0	1	0

Bits 7:6 – ENTO[1:0] (EN) timeout delay programming bits

Default is 00 (0 seconds).

Bits 5:4 – ENINTTO[1:0] EN interrupt assertion timeout delay programming bits

Default is 01 (0.5 second).

Bit 3 – Reserved

Maintain as ‘0’

Bits 2:0 – RSTDLY[2:0] nRSTO assertion delay programming bits (t₄ in the start-up sequence)

Default is 010 (4 ms).

DS20007136A

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

2.6.4 System Timing Settings

Bits 7:6 – ENTO[1:0] (EN) timeout delay programming bits

Bits 5:4 – ENINTTO[1:0] EN interrupt assertion timeout delay programming bits

Bit 3 – Reserved

Bits 2:0 – RSTDLY[2:0] nRSTO assertion delay programming bits (t4 in the start-up sequence)

Bits 2:0 – RSTDLY[2:0] nRSTO assertion delay programming bits (t₄ in the start-up sequence)