2.6.1 Register Summary
| Address | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
| System Registers | ||||||||||
| 0x00 | SYS-ADR | 7:0 | Reserved | ADR[6:2] | ADR[1:0] | |||||
| 0x01 | SYS-ID | 7:0 | ID[3:0] | REV[3:0] | ||||||
| 0x02 | SYS-TMG | 7:0 | ENTO[1:0] | ENINTTO[1:0] | Reserved | RSTDLY[2:0] | ||||
| 0x03 | SYS-CFG | 7:0 | TSDMSK | TWRMSK | HPMPEN | AWKPDIS | FSD [1:0] | B1HCEN | USER | |
| System and Power Channels Status Registers | ||||||||||
| 0x04 | STS-SYS | 7:0 | TSD | TWR | ENINT | STRTF | Reserved[3:0] | |||
| 0x05 | STS-B1 | 7:0 | FLT | HICCUP | ILIMNEG | ZCD | Reserved | SSD | POK | ENS |
| 0x06 | STS-B2 | 7:0 | FLT | HICCUP | ILIMNEG | ZCD | Reserved | SSD | POK | ENS |
| 0x07 | STS-B3 | 7:0 | FLT | HICCUP | ILIMNEG | ZCD | Reserved | SSD | POK | ENS |
| 0x08 | STS-B4 | 7:0 | FLT | HICCUP | ILIMNEG | ZCD | Reserved | SSD | POK | ENS |
| 0x09 | STS-L1 | 7:0 | FLT | Reserved[2:0] | ILIM | SSD | POK | ENS | ||
| 0x0A | STS-L2 | 7:0 | FLT | Reserved[2:0] | ILIM | SSD | POK | ENS | ||
| Buck1 Regulator Setup | ||||||||||
| 0x10 | OUT1-A | 7:0 | EN | MODE | VSET[5:0] | |||||
| 0x11 | OUT1-LPM | 7:0 | EN | MODE | VSET[5:0] | |||||
| 0x12 | OUT1-HIB | 7:0 | EN | MODE | VSET[5:0] | |||||
| 0x13 | OUT1-HPM | 7:0 | EN | MODE | VSET[5:0] | |||||
| 0x14 | OUT1-SEQ | 7:0 | SSR[1:0] | SEQ[1:0] | SEQEN | DELAY[2:0] | ||||
| 0x15 | OUT1-CFG | 7:0 | FLTMSK | HCPEN | DISCH | PHASE | DVSR[1:0] | REN | RCON | |
| Buck2 Regulator Setup | ||||||||||
| 0x20 | OUT2-A | 7:0 | EN | MODE | VSET[5:0] | |||||
| 0x21 | OUT2-LPM | 7:0 | EN | MODE | VSET[5:0] | |||||
| 0x22 | OUT2-HIB | 7:0 | EN | MODE | VSET[5:0] | |||||
| 0x23 | OUT2-HPM | 7:0 | EN | MODE | VSET[5:0] | |||||
| 0x24 | OUT2-SEQ | 7:0 | SSR[1:0] | SEQ[1:0] | SEQEN | DELAY[2:0] | ||||
| 0x25 | OUT2-CFG | 7:0 | FLTMSK | HCPEN | DISCH | PHASE | DVSR[1:0] | REN | RCON | |
| Buck3 Regulator Setup | ||||||||||
| 0x30 | OUT3-A | 7:0 | EN | MODE | VSET[5:0] | |||||
| 0x31 | OUT3-LPM | 7:0 | EN | MODE | VSET[5:0] | |||||
| 0x32 | OUT3-HIB | 7:0 | EN | MODE | VSET[5:0] | |||||
| 0x33 | OUT3-HPM | 7:0 | EN | MODE | VSET[5:0] | |||||
| 0x34 | OUT3-SEQ | 7:0 | SSR[1:0] | SEQ[1:0] | SEQEN | DELAY[2:0] | ||||
| 0x35 | OUT3-CFG | 7:0 | FLTMSK | HCPEN | DISCH | PHASE | DVSR[1:0] | REN | RCON | |
| Buck4 Regulator Setup | ||||||||||
| 0x40 | OUT4-A | 7:0 | EN | MODE | VSET[5:0] | |||||
| 0x41 | OUT4-LPM | 7:0 | EN | MODE | VSET[5:0] | |||||
| 0x42 | OUT4-HIB | 7:0 | EN | MODE | VSET[5:0] | |||||
| 0x43 | OUT4-HPM | 7:0 | EN | MODE | VSET[5:0] | |||||
| 0x44 | OUT4-SEQ | 7:0 | SSR[1:0] | SEQ[1:0] | SEQEN | DELAY[2:0] | ||||
| 0x45 | OUT4-CFG | 7:0 | FLTMSK | HCPEN | DISCH | PHASE | DVSR[1:0] | REN | RCON | |
| LDO1 Setup | ||||||||||
| 0x50 | LDO1-A | 7:0 | EN | Reserved | VSET[5:0] | |||||
| 0x51 | LDO1-LPM | 7:0 | EN | Reserved | VSET[5:0] | |||||
| 0x52 | LDO1-HIB | 7:0 | EN | Reserved | VSET[5:0] | |||||
| 0x53 | LDO1-HPM | 7:0 | EN | Reserved | VSET[5:0] | |||||
| 0x54 | LDO1-SEQ | 7:0 | SSR[1:0] | SEQ[1:0] | SEQEN | DELAY[2:0] | ||||
| 0x55 | LDO1-CFG | 7:0 | FLTMSK | Reserved | DISCH | Reserved | DVSR[1:0] | REN | RCON | |
| LDO2 Setup | ||||||||||
| 0x60 | LDO2-A | 7:0 | EN | Reserved | VSET[5:0] | |||||
| 0x61 | LDO2-LPM | 7:0 | EN | Reserved | VSET[5:0] | |||||
| 0x62 | LDO2-HIB | 7:0 | EN | Reserved | VSET[5:0] | |||||
| 0x63 | LDO2-HPM | 7:0 | EN | Reserved | VSET[5:0] | |||||
| 0x64 | LDO2-SEQ | 7:0 | SSR[1:0] | SEQ[1:0] | SEQEN | DELAY[2:0] | ||||
| 0x65 | LDO2-CFG | 7:0 | FLTMSK | Reserved | DISCH | Reserved | DVSR[1:0] | REN | RCON | |