2.6.6 System Status
| Name: | STS-SYS |
| Address: | 0x04 |
| Default: | 0x00 |
| Property: | R/RoR |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TSD | TWR | ENINT | STRTF | Reserved[3:0] | |||||
| Access | R/RoR | R/RoR | R/RoR | R | R | R | R | R | |
| Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 7 – TSD Thermal Shutdown Fault Flag (latched)
If a Thermal Shutdown occurs, TSD bit will be set to 1. It will not automatically return to 0 after the Thermal Shutdown condition has ceased. If the fault condition is no longer present, a READ operation will automatically also clear the flag (Reset-on-Read, RoR).
If the corresponding masking bit TSDMSK is 0, TSD = 1 will cause nINTO being asserted LOW.
Bit 6 – TWR Thermal Warning Fault Flag (latched)
If a Thermal Warning occurs, TWR bit will be set to 1. It will not automatically return to 0 after the Thermal Warning condition has ceased. If the fault condition is no longer present, a READ operation will automatically also clear the flag (Reset-on-Read, RoR).
If the corresponding masking bit TWRMSK is 0, TWR = 1 will cause nINTO being asserted LOW
Bit 5 – ENINT Interrupt flag
This bit is set as soon as the Enable timeout has expired. A read action will reset the ENINT flag and also reset the Enable timeout counter.
Bit 4 – STRTF Start-Up Fail Flag
If MCP16503 has counted 5 invalid Start-Up, this flag will be set. This flag will be automatically reset when EN = 0 has been detected when the IC is in OFF mode or at a power cycle or at any valid Start-Up. The IC will stay in OFF mode until the counter is reset.