2.6.36 Buck4 Configuration

Name: OUT4-CFG
Address: 0x45
Default: 0xA0
Property: R/W

Bit 76543210 
 FLTMSKHCPENDISCHPHASEDVSR[1:0]RENRCON 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Default 10100000 

Bit 7 – FLTMSK Fault Masking bit

If the bit is 1, it will prevent nINTO from being asserted LOW upon FLT = 1.

Bit 6 – HCPEN Short-Circuit Protection Hiccup Mode Enable

If HCPEN = 1, a short-circuit event will cause hiccup-mode response with unlimited Soft-Start retries, without shutting down the other channels. If HCPEN = 0, a short circuit event on the channel will cause immediate shutdown of ALL channels, and a new Start-Up Sequence will automatically be attempted after a 100 ms delay.

Bit 5 – DISCH Active Output Discharge Control

DISCH = 1 enables Active Output Discharge when a channel is turned OFF, DISCH = 0 disables it.

Bit 4 – PHASE Regulator Phase Control

Setting the bit to 1 will cause the regulator to operate 180° out of phase with the oscillator, and clearing the bit to 0 will cause the regulator to operate in phase with the oscillator.

Bits 3:2 – DVSR[1:0] Dynamic Voltage Scaling Rate programming bits

Bit 1 – REN Register Enable Bit

Used in combination with RCON:

If RCON = 0, the value of REN has no effect.

If RCON = 1, setting REN = 1 enables channel and setting REN = 0 disables it, regardless of the current Status.

Mode of operation (FPWM or Auto-PFM) is still controlled by the MODE bits.

Bit 0 – RCON Register Enable Control Bit

Used in combination with REN:

If RCON = 0, the value of REN has no effect.

If RCON = 1, setting REN = 1 enables channel and setting REN = 0 disables it, regardless of the current Status.

Mode of operation (FPWM or Auto-PFM) is still controlled by the MODE bits.